USB is an industry protocol designed to standardize interfaces between computer devices for communication and supplying electrical power. The USB2 protocol has enjoyed widespread adoption in nearly every computing device, and has received tremendous support in terms of technology development with well-established standardized software infrastructure. The standard USB2 specification uses 3.3V analog signaling for communications between the two USB2 ports. The 3.3V signal strength tends to introduce integration challenges because some advanced semiconductor processes are moving towards a very low geometry leading to the gate oxide of a CMOS transistor no longer able to tolerate higher voltages, such as 3.3V. Embedded USB2 (eUSB2) provides a solution for future generation system on chip (SOC) designs in which a repeater handles high voltage operation during a classical speed mode of operation, and operates as a re-driver during high speed operation. eUSB2 defines a protocol for communication between the PHY and repeater based on the USB2 operation.
Power gating is a widely accepted technique for managing power. However, there are challenges in implementing power gating for a eUSB2 PHY and repeater. One problem is that power gating both the SOC and repeater results in a latency problem. Since both the SOC PHY and repeater need to perform a configuration Signaling (TbConfig) process to indicate a top down (host/device configuration) indication plus a SE1 Signaling referred as TSE1 process to make an announcement between the SOC PHY and Repeater. Aggressive Power gating will not be able to meet a 1 ms latency requirement during remote wake where the eUSB2 system (including repeater and Controller) needs to wake and reflect Resume-K within 1 ms). The impact of not power gating results in ˜300 uW for 1× port and ˜1.2 mW for 8× ports configuration.
Another challenge is presented when attempting to meet latency requirements during a lower power state. For instance, the SOC PHY is already in power gated mode, and the repeater is also in power gated mode, except wake on connect. In such instances the SOC eUSB2 PHY will suffer from back power (e.g., back current flow from the repeater to the SOC eUSB2 PHY) current during repeater periodically announcing a wake presence to check presence of the SOC eUSB2 PHY. This back power results in reliability issues. Finally, power gating the repeater will impact USB2 functionality, and is thus not a viable solution.